Signal transition time is defined as the delay between two points during the change of a logical value. The two points are commonly defined at 10% and 90% of the power voltage. FIG. 1 illustrates an example of a rising signal transition. Signal transition times can vary in logic designs such as ASIC, structured ASIC, field programmable gate array (FPGA), and printed circuit board (PCB) products. Depending on the input waveform, capacitive loading, the nature of the driving logic element, and traveling distance of a signal, the transition time of the signal can vary ten times or even more on a given chip.
Signal transition times can impact the timing and power consumption of logic designs in several ways. For example, the delay of combinational and sequential logic elements along a signal path (signal delay) is a function of signal transition time. Also, during signal transition time, both p and n MOSFETs in CMOS logic are open which creates a short circuit path between power and ground. Thus, modeling and controlling signal transition times on an logic design is desirable from a timing and power stand point.
In the past, EDA tools were forced to adhere to signal integrity rules by observing indirect constraints, such as maximum fan-out limitations and maximum capacitive loading limitations. This was followed by post-processing procedures that attempted to fix violations in the routed design by inserting new buffers or upsizing existing buffers. This resulted in sub-optimal designs.
Thus, what is needed is an efficient method and apparatus for integrating signal transition time modeling during routing in an EDA tool.